1. Field of the Invention
The present invention generally relates to semiconductor chips and methods of manufacturing semiconductor chips, and particularly relates to a semiconductor chip and a method of manufacturing a semiconductor chip that is provided with a through via penetrating through the semiconductor substrate and electrode pads.
2. Description of the Related Art
Keeping pace with the recent sophistication and miniaturization of electronic devices, there has been progress in the development of multi-chip packages in which a plurality of semiconductor chips are stacked one over another. Semiconductor chips used in multi-chip packages have a through via that is electrically connected to other semiconductor chips disposed on its top and beneath its bottom. Such through via includes one that is formed to penetrate through the semiconductor substrate and an electrode pad as shown in FIG. 1.
FIG. 1 is a cross-sectional view of a related-art semiconductor chip.
As shown in FIG. 1, a semiconductor chip 100 includes a semiconductor substrate 101, a semiconductor-device layer 102 in which semiconductor devices (not shown) are formed, an electrode pad 103, a conductive metal member 104, an insulating film 106, a metal layer 108, and a through via 111.
A through hole 112 that penetrates through the semiconductor-device layer 102, the electrode pad 103, and the conductive metal member 104 is formed in the semiconductor substrate 101. The electrode pad 103 is electrically connected to the conductive metal member 104 and a semiconductor device (not shown). The conductive metal member 104 serves to protect the electrode pad 103 from damage when forming an opening part 106A through the insulating film 106 by laser processing.
The insulating film 106 is formed to cover the back surface 101A of the semiconductor substrate 101, the conductive metal member 104, and the through hole 112. The insulating film 106 has the opening part 106A that exposes an upper surface 104A of the conductive metal member 104.
The metal layer 108 is provided such as to cover the side wall of the through hole 112 on which the insulating film 106 is formed, and also to fill the opening part 106A.
The through via 111 is situated in the through hole 112 that has the insulating film 106 and the metal layer 108 formed therein. The through via 111 is electrically connected to the electrode pad 103 via the metal layer 108 and the conductive metal member 104. The through via 111 is formed by use of an electroplating method for which the metal layer 108 is used as a power feeding layer.
The semiconductor chip 100 having such a configuration as describe above is electrically connected to another semiconductor chip through solder that is deposited on a tip of the through via 111 (see Patent Document 1, for example).
[Patent Document 1] Japanese Patent Application Publication No. 2002-373895
In the semiconductor chip 100 having a conventional structure as described above, however, the conductive metal member 104 and/or the metal layer 108 are provided to electrically connect the electrode pad 103 with the through via 111, giving rise to the problem of cost increases.
Further, the provision of the conductive metal member 104 and the metal layer 108 adds to the complexity of the process of manufacturing the semiconductor chip 100, resulting in a problem that the manufacturing cost of the semiconductor chip 100 increases.
Moreover, the provision of the conductive metal member 104 results in the deepening of the through hole 112, which elongates the time of the electroplating process for forming the through via 111. This also increases the manufacturing cost of the semiconductor chip 100.
It should also be noted that the through via 111 is formed through the deposition and growth of conductive metal on the metal layer 108 formed on the insulating film 106. Because of this, there is a problem in that a void may be created at the center of the through via 111.
Accordingly, there is a need for a semiconductor chip and a method of manufacturing the semiconductor chip that can avoid the generation of a void in the through via and can also reduce the cost inclusive of the manufacturing cost.